Wireless digital communications often involves transmission of symbols using a modulated carrier and the subsequent coherent demodulation of the modulated carrier by a receiver. One way to perform coherent demodulation is to synchronize the receiver's local carrier with the modulated carrier using a phase locked loop (PLL). PLLs attempt to eliminate the phase error between the modulated carrier and the local carrier. One component of a PLL is a phase detector.
In digital communications, and particularly in mobile digital communications, it is beneficial to employ circuitry that is fast, inexpensive, relatively simple, and power efficient. Accordingly, research and development continue into improving the designs of PLLs.